Low-Power Design and Power-Aware Verification by Progyna Khondkar

Author:Progyna Khondkar
Language: eng
Format: epub, pdf
Publisher: Springer International Publishing, Cham

4.2.2 PA-Simulation Model Library

On the contrary, a PA-Simulation Model library completely represents all the power, ground, bias, and related supply ports or PG-pins of a cell. As well it defines the power down functionalities. The PG-pins in PA-Simulation Models are primarily defined as input and output ports; however they may also be defined as internal registers, wires, or as supply_net_type, supply0 and supply1 type etc. Although the internal types of PG-pins are more common in an extended PA-Simulation Model library explained in the next section.

The PA-Simulation Model also includes the behavioral code that monitors the supply ports and appropriately corrupts its internal states and outputs, in response to events or values on the power supply and logic ports. However, the explicit connection of an external testbench and UPF power supply to these PA model’s supply ports is mandatory through UPF connect_supply_net or connect_supply_set explicit commands. The explicit UPF connections disable the simstate-based corruption semantics, unlike non-PA models explained in the previous section. Hence Questa® power aware simulator or PA-SIM allows the PA-Simulation Model library (.v) to take precedence and apply corruption semantics by itself. The simulator drives only the appropriate supply values to the PG-pin of the cell — when VDD is turned off (Example 4.6), the output Y will become 1’bx.

Obviously a corresponding Liberty (.lib) library is unnecessary for PA verification with PA-Simulation Model library. The PA-Simulation Models are more suitable for modelling multi-rail macros and specifically they are created for PA simulation-based verification at the post place-and-route PG-netlist level, since PG-netlists contain PG-pin connectivity as well as the logical functionality of a cell.

Questa® PA-SIM also supports UPF predefined attribute-based automatic connections, if a supply port has the UPF_pg_type attribute associated with it — either by an HDL attribute specification or a UPF set_port_attributes command, based upon its pg_type. In this case, the appropriate value conversion table (VCT) will also be inserted based on the pg_type of the port.

Example 4.8 UPF Predefined Attributes Usage in HDL

For VHDL: attribute UPF_pg_type of vdd_backup: signal is "backup_power"

For System Verilog: (* UPF_pg_type = “backup_power” *) input vdd_backup;

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